Beyond-CMOS VLSI (Future Technology after Silicon)

Abstract

The scaling of traditional CMOS technology based on silicon is rapidly reaching physical and economical
limits for deeplyscaled nodes below 5 nm, as has been expounded in various recent works on scaling
options [1], [3]. The presence of short-channel effects, high power density, variability, and interconnect
limitations has made the pursuit of Beyond-CMOS device options imperative, as has already been discussed
for sub-5 nm nodes [1], [4]. This paper seeks to provide a comprehensive comparison and assessment of
recent efforts on advanced CMOS technologies, two-dimensional material transistors, Tunnel Field Effect
Transistors, and two-dimensional magnetic heterostructures for spintronics and quantum computing, as has
appeared in various recent surveys on the topic. Through a validation of scalability, possible trade-offs for
power and performance, manufacturability, and CMOS integration, the paper argues that a heterogeneous
integration strategy that packages more than one device technology holds the most promise for maintaining
Moore's scaling momentum [1], [15]. Notably, the need for such scaling is highly relevant for modern VLSI
systems, because scaling directly affects the reliability, energy efficiency, yields, and overall system
performance, as has appeared consistently in the literature on the topic [1], [18]. Moreover, with further
scaling, previously sub-dominant physical phenomena are increasingly governing device operations,
necessitating innovations at both the materials and architectural levels [3], [4]